Fr. 188.00

Creating Assertion-Based IP

Anglais · Livre Relié

Expédition généralement dans un délai de 2 à 3 semaines (titre imprimé sur commande)

Description

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Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user's existing verification environment, in other words the testbench infrastructure.

The guiding principles promoted in this book when creating an assertion-based IP monitor are:


  • modularity-assertion-based IP should have a clear separation between detection and action

  • clarity-assertion-based IP should be written initially focusing on capturing intent (versus optimizations)


A unique feature of this book is the fully worked out, detailed examples. The concepts presented in the book are drawn from the authors' experience developing assertion-based IP, as well as general assertion-based techniques. Creating Assertion-Based IP is an important resource for design and verification engineers.
From the Foreword:

Creating Assertion-Based IP "...reduces to process the creation of one of the most valuable kinds of VIP: assertion-based VIP...This book will serve as a valuable reference for years to come."

Andrew Piziali, Sr. Design Verification Engineer
Co-Author, ESL Design and Verification: A Prescription for Electronic System Level Methodology
Author, Functional Verification Coverage Measurement and Analysis

Table des matières

Foreword.- Preface.- Introduction.- Definitions and Terminology.- The Process.- Bus-Based Design Example.- Interfaces.- Arbiters.- Controllers.- Datapath Units.

Résumé

Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user’s existing verification environment, in other words the testbench infrastructure.

The guiding principles promoted in this book when creating an assertion-based IP monitor are:

modularity—assertion-based IP should have a clear separation between detection and action
clarity—assertion-based IP should be written initially focusing on capturing intent (versus optimizations)

A unique feature of this book is the fully worked out, detailed examples. The concepts presented in the book are drawn from the authors’ experience developing assertion-based IP, as well as general assertion-based techniques. Creating Assertion-Based IP is an important resource for design and verification engineers.
From the Foreword:

Creating Assertion-Based IP "…reduces to process the creation of one of the most valuable kinds of VIP: assertion-based VIP…This book will serve as a valuable reference for years to come."Andrew Piziali, Sr. Design Verification EngineerCo-Author, ESL Design and Verification: A Prescription for Electronic System Level MethodologyAuthor, Functional Verification Coverage Measurement and Analysis

Détails du produit

Auteurs Harry Foster, Harry D Foster, Harry D. Foster, Adam C Krolnik, Adam C. Krolnik
Edition Springer, Berlin
 
Langues Anglais
Format d'édition Livre Relié
Sortie 10.12.2007
 
EAN 9780387366418
ISBN 978-0-387-36641-8
Pages 318
Dimensions 155 mm x 21 mm x 235 mm
Poids 613 g
Illustrations XVIII, 318 p.
Thèmes Series on Integrated Circuits and Systems
Integrated Circuits and Systems
Series on Integrated Circuits and Systems
Integrated Circuits and Systems
Catégorie Sciences naturelles, médecine, informatique, technique > Technique > Electronique, électrotechnique, technique de l'information

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