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Presents a range of CAD algorithms and techniques for synthesizing and optimizing interconnect
Provides insight & intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits
Table des matières
Introduction.- Noise Analysis and Design in Deep Submicron.- Interconnect Noise Analysis and Optimization Techniques.- Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies.- Minimum Area Shield Insertion for Inductive Noise Reduction.- Spacing Algorithms for Crosstalk Noise Reduction.- Post Layout Interconnect Optimization for Crosscoupling Noise Reduction.- 3D Integration. - EDA Industry Tools: State of the Art.
Résumé
Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.
The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.
