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This Book presents the design, optimisation and physical implementation of a twodimensional
(2D) discrete wavelet transform (DWT) image processor using the residue
number system (RNS), and examines it against an initial processor designed based on
existing binary modules. The original contributions of the proposed design include a
low-complexity hardware architecture of the RNS-based filter banks, optimised transposition
units, and exploitation of the multi-voltage scheme to reduce the power consumption.
Modular adders and multipliers of the RNS-based filter banks are simplified
to save on hardware complexity, while modular arithmetic and 6-bit dyadic-fraction
filter coefficients are applied to improve the system performance. The proposed design
is synthesised with the Synopsys 90 nm Generic Library (SAED90nmEDK) using
the Synopsys synthesis and implementation tools. The synthesis results show that
the proposed RNS-based processor is 23% faster than the initial processor. Another
noteworthy result is that the total area of the RNS-based processor is less than the
total area in the initial binary processor. It confirms that using the proposed architecture
for RNS-based filter banks has saved on the hardware complexity and the system
area requirement. The proposed RNS-based processor is implemented using the multivoltage
(MV) low power design (LPD) scheme to improve the power performance of
the proposed processor. The power synthesis results show that using the multi-voltage
scheme reduces the total power of the proposed RNS-based design by up to 50%. The
proposed residue arithmetic units are explained in details to illustrate the novelty of
the proposed design.
