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Thisbook provides a hands-on, application-oriented guide to the language andmethodology of both SystemVerilog Assertions and SystemVerilog FunctionalCoverage. Readers will benefit from the step-by-step approach to functionalhardware verification using SystemVerilog Assertions and Functional Coverage,which will enable them to uncover hidden and hard to find bugs, point directlyto the source of the bug, provide for a clean and easy way to model complextiming checks and objectively answer the question 'have we functionallyverified everything'. Written by a professional end-user of ASIC/SoC/CPU andFPGA design and Verification, this book explains each concept with easy tounderstand examples, simulation logs and applications derived from realprojects. Readers will be empowered to tackle the modeling of complex checkersfor functional verification, thereby drastically reducing their time to designand debug.
This updated second edition addresses the latest functional set releasedin IEEE-1800 (2012) LRM, including numerous additional operators and features.Additionally, many of the Concurrent Assertions/Operators explanations areenhanced, with the addition of more examples and figures.
· Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics;
· Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage language and methodologies;
· Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies;
· Explains each concept in a step-by-step fashion and applies it to a practical real life example;
· Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.
Inhaltsverzeichnis
Introduction.- System Verilog Assertions.- Immediate Assertions.- Concurrent Assertions - Basics (sequence, property, assert).- Sampled Value Functions $rose, $fell.- Operators.- System Functions and Tasks.- Multiple clocks.- Local Variables.- Recursive property.- Detecting and using endpoint of a sequence.- 'expect'.- 'assume' and formal (static functional) verification.- Other important topics.- Asynchronous Assertions !!!.- IEEE-1800-2009 Features.- SystemVerilog Assertions LABs.- System Verilog Assertions - LAB Answers.- Functional Coverage.- Performance Implications of coverage methodology.- Coverage Options.
Über den Autor / die Autorin
Ashok Mehta has been working in the ASIC/SoC design and verification
field for over 20 years. He started his career at Digital Equipment Corporation
(DEC) working first as a CPU design engineer, moving on to hardware design verification
of the VAX11-785 CPU design. He then worked at Data General, Intel (first
Pentium design team) and after a route of a couple of startups, worked at
Applied Micro and TSMC. He was a very early adopter of Verilog and participated
in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees.
He has also been a proponent of ESL (Electronic System Level) designs and at
TSMC he released two industry standard Reference Flows that take designs from
ESL to RTL while preserving the verification environment for reuse from ESL to
RTL. Lately, he has been involved with 3DIC design verification challenges at
TSMC which is where SystemVerilog Assertions played an instrumental role in
stacked die SoC design verification.
Ashok earned an MSEE from University
of Missouri. He holds 13 U.S. Patents in the field of SoC and 3DIC design
verification.
Zusammenfassung
This
book provides a hands-on, application-oriented guide to the language and
methodology of both SystemVerilog Assertions and SystemVerilog Functional
Coverage. Readers will benefit from the step-by-step approach to functional
hardware verification using SystemVerilog Assertions and Functional Coverage,
which will enable them to uncover hidden and hard to find bugs, point directly
to the source of the bug, provide for a clean and easy way to model complex
timing checks and objectively answer the question ‘have we functionally
verified everything’. Written by a professional end-user of ASIC/SoC/CPU and
FPGA design and Verification, this book explains each concept with easy to
understand examples, simulation logs and applications derived from real
projects. Readers will be empowered to tackle the modeling of complex checkers
for functional verification, thereby drastically reducing their time to design
and debug.
This updated second edition addresses the latest functional set released
in IEEE-1800 (2012) LRM, including numerous additional operators and features.
Additionally, many of the Concurrent Assertions/Operators explanations are
enhanced, with the addition of more examples and figures.· Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics;· Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage language and methodologies;· Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies;· Explains each concept in a step-by-step fashion and applies it to a practical real life example;· Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.
