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This book provides the comprehensive and in-depth coverage of the circuit design developments in millimeter-wave (mm-wave) CMOS phase-locked loop (PLL). PLL is the key component in a transceiver and is widely used in the mm-wave applications including 60 GHz high data rate communication, 24/77 GHz automotive radar, 94 GHz mm-wave imaging, and so on. Although CMOS technology still encounters the problems of poor performance, high substrate loss, and inaccurate model at mm-wave frequency, mm-wave CMOS PLL is always expected due to its low cost and compatibility with CMOS digital circuits. This book contains both circuit-level and system-level coverage that provide deep practical insight in high frequency, wide locking range, low phase noise, and low power mm-wave CMOS PLL building blocks and systems design.
Über den Autor / die Autorin
Dr. Yi Xiang received the Ph.D. degree from Nanyang Technological University. His research interests include radio frequency (RF) and millimetre-wave (mm-wave) phase-locked loops (PLLs) and transceiver systems. He was the recipient of the IEEE ISSCC Silkroad Award and SSCS Travel Grant Award and in 2013.
