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Informationen zum Autor José Duato received MS and PhD degrees in electrical engineering from the Universidad Politecnica de Valencia, Spain, in 1981 and 1985. Currently, Dr. Duato is Professor in the Department of Computer Engineering (DISCA), and adjunct professor in the Department of Computer and Information Science, The Ohio State University. His current research interests include high-speed interconnects, multiprocessor architectures, cluster architectures, and IP routers. Dr. Duato proposed the first theory of deadlock-free adaptive routing for wormhole networks. This theory has been used in the design of the routing algorithms for the MIT Reliable Router, the Cray T3E router, and the on-chip router of the Alpha 21364 microprocessor. Dr. Duato is currently collaborating with IBM on the design of the interconnection network for the IBM BlueGene/L supercomputer, and on the next generation of the IBM PRIZMA switch for IP routers. Dr. Duato served as a member of the editorial board of IEEE Transactions on Parallel and Distributed Systems and he is currently serving as associate editor of IEEE Transactions on Computers. He has been the General Co-Chair for the 2001 International Conference on Parallel Processing. Also, he served as Co-Chair, member of the Steering Committee, Vice-Chair, or member of the Program Committee in more than 30 conferences, including the most prestigious conferences in his field (HPCA, ISCA, IPPS/SPDP, ICPP, ICDCS, Europar, HiPC). Klappentext The performance of most digital systems today is limited by their communication or interconnection, not by their logic or memory. As designers strive to make more efficient use of scarce interconnection bandwidth, interconnection networks are emerging as a nearly universal solution to the system-level communication problems for modern digital systems. Interconnection networks have become pervasive in their traditional application as processor-memory and processor-processor interconnect. Point-to-point interconnection networks have replaced buses in an ever widening range of applications that include on-chip interconnect, switches and routers, and I/O systems. In this book, the authors present in a structured way the basic underlying concepts of most interconnection networks and provide representative solutions that have been implemented in the industry or proposed in the research literature. Zusammenfassung The performance of most digital systems is limited by their communication or interconnection! not by their logic or memory. Interconnection networks have become pervasive in their traditional application as processor-memory and processor-processor interconnect. This book presents the basic underlying concepts of most interconnection networks. Inhaltsverzeichnis ForewordForeword to the First PrintingPrefaceChapter 1 - IntroductionChapter 2 - Message Switching LayerChapter 3 - Deadlock, Livelock, and StarvationChapter 4 - Routing AlgorithmsChapter 5 - CollectiveCommunicationSupportChapter 6 - Fault-Tolerant RoutingChapter 7 - Network ArchitecturesChapter 8 - Messaging Layer SoftwareChapter 9 - Performance EvaluationAppendix A - Formal Definitions for Deadlock AvoidanceAppendix B - AcronymsReferencesIndex...
