Fr. 134.00

Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies

Inglese · Copertina rigida

Spedizione di solito entro 2 a 3 settimane (il titolo viene stampato sull'ordine)

Descrizione

Ulteriori informazioni

In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.

Sommario

TO LOW-POWER DIGITAL INTEGRATED CIRCUIT DESIGN.- LOGIC WITH MULTIPLE SUPPLY VOLTAGES.- LOGIC WITH MULTIPLE THRESHOLD VOLTAGES.- FORCING OF TRANSISTOR STACKS.- POWER GATING.- CONCLUSION.

Riassunto

In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.

Dettagli sul prodotto

Autori Stephan Henzler
Editore Springer Netherlands
 
Lingue Inglese
Formato Copertina rigida
Pubblicazione 01.07.2009
 
EAN 9781402050800
ISBN 978-1-4020-5080-0
Pagine 186
Dimensioni 160 mm x 17 mm x 246 mm
Peso 420 g
Illustrazioni XVI, 186 p.
Serie Springer Series in Advanced Microelectronics
Springer Series in Advanced Microelectronics
Categoria Scienze naturali, medicina, informatica, tecnica > Tecnica > Elettronica, elettrotecnica, telecomunicazioni

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