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The major difficulty in carrying out the performance analysis of a hardware system like Hardware Transactional Memory lies in suitably modeling it. The model should be very close to the actual proposed hardware. FPGAs are a good platform for doing so but they have a huge development time associated with them. Software simulators on the other hand are very convenient, easy to use and time-saving tools but they are not good enough to gather time accurate performance statistics which is very critical for the performance analysis of any proposed hardware system. In this work we propose the use of multicore multithreaded processor platforms from XMOS Ltd. for performance analysis, which are easily programmable in a high level language like C. They can be effectively used to build close-to-prototype models, and can therefore act as a good common base for comparison of various similar hardware systems. Although, this work specifically details the performance analysis of a Hardware Transactional memory system on the XMOS platform, the methodology can be generically applied to a variety of systems.
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Prabhat Jain received the MS degree in Computer Science from University of Illinois at Urbana-Champaign in 2012. He also holds a bachelor's degree in Computer Science and Engineering from the Indian Institute of Technology Madras. His interests broadly lie in Systems research and development with particular interest in Computer Architecture.
