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The speed gap between a processor realized in Semi-custom ASIC technology and a processor realized in FPGA technology is narrowing. Common pracatise is to define and design the microarchitecture of the processor for executing an application domain. We investigate the reverse approach to design a customized and parameterized VLIW processor for a fingerprint application. We analyze the applications requirements before porting it to run on the VEX simulator. This required design and integration of an arithmetic module for emulating 64-bit arithmetic. From the ported application on the VEX simulator we derive the architectural parameters for the VEX processor. Based on these, we designed a pipelined and parametrized VLIW processor according to the VEX ISA. Moreover, this design was implemented and realized in a Virtex-6 FPGA. Furthermore, creating the instruction memory of the VEX processor required the development of a toolchain that was inherited from the -VEX project. For this purpose, we extended the back-end of the VEX compiler, re-designed the assembler and developed a linker with a loader. The toolchain allowed us to process the fingerprint application s kernel on the VEX CPU.
Info autore
Roël A.E. Seedorf was born on 7 september 1977 in Paramaribo Suriname. In september 1999 he started his Electrical Engineering studies at the TU Delft. He obtained a BSc degree in Electrical Engineering and his Master of Science Degree in Computer Engineering. Now he is involved in the EU Embedded Reconfigurable architectures Research Project ERA.
