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In recent years, down scaling in CMOS advanced technologies has provided high performance in the digital circuits and reduced cost thereby meeting to a large extent the increasing demand of wireless communication products. With this technology advancement, the unity-current gain frequency of CMOS technology is now over several tens of GHz making the realization of system on-chip solution possible which turns to further reduced cost. The concept of the RFIC design needed for the design of low noise amplifier such as gain, noise, stability, linearity, power consumption etc is discussed in the report. An overview has been given on different LNA architecture, their advantages and disadvantages have also been discussed.The designed circuit is simulated with the help of specture simulator from cadence design system using UMC .18um CMOS technology. After the simulation we got the simulated result of low noise amplifier as forward voltage gain(S21) of 18.53dB, noise figure is 1.8dB and minimum noise figure is 1.6dB, input reflection coefficient (S11) is -24dB, output reflection coefficient(S22) is -15dB,stability factor (Kf) is 4, IIP3 -10 dBm by using power supply voltage of 1.8v.
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Mr Jitendra Mishra obtained his Bachelor of Technology from A.I.T.H,Kanpur (india)in 2010. He obtained his Master Degree from National Institute of Technology,Silchar(India)in 2013.He is currently working as Asst Prof in Royal Group Of Institution,Guwhati(India).
