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High-Speed Serial Interface (HSSI) devices have become widespread in communications, from the embedded to high-performance computing systems, and from on-chip to a wide haul. Testing of HSSIs has been a challenging topic because of signal integrity issues, long test time and the need of expensive instruments. Accelerating Test, Validation and Debug of High Speed Serial Interfaces provides innovative test and debug approaches and detailed instructions on how to arrive to practical test of modern high-speed interfaces.
Accelerating Test, Validation and Debug of High Speed Serial Interfaces first proposes a new algorithm that enables us to perform receiver test more than 1000 times faster. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms, while the test usually takes seconds. The book also presents and external loopback-based testing scheme, where and FPGA-based BER tester and a novel jitter injection technique are proposed. These schemes can be applied to validate, test and debug HSSIs with data rate up to 12.5Gbps at a lower test cost than pure ATE solutions. In addition, the book introduces an efficieng scheme to implement high performance Gaussian noise generators, suitable for evaluating BER performance under noise conditions.
List of contents
1 Introduction. 2 Background. 3 Accelerating Receiver Jitter Tolerance Testing on ATE. 4 Transmitter Jitter Extractions on ATE. 5 Testing HSSIs with or without ATE Instruments. 6 BER Testing Under Noise. 7 Conclusions. Reference. Index.
About the author
Yongquan Fan is a Senior Test Engineer in the High Performance Analog group at Texas Instruments. He had been a Senior Staff Engineer in the Storage Peripheral Group at LSI Corporation from 2003~2008. From 1991 to 2000, he worked for Sichuan Changhong Electronic Incorporation, China. Yongquan Fan obtained his Ph.D and MENG degree from McGill University, Canada and his BS from Beijing University of Aeronautics and Astronautics, China, all in Electrical Engineering.
Zeljko Zilic received his Ph. D. and M. Sc. from the University of Toronto, and his B. Eng. from University of Zagreb, Croatia. From 1996 till 1997 he worked for Lucent Microelectronics. He joined McGill University in 1998, where he is now an Associate Professor. Prof. Zilic has used a sabbatical leave in 2004/2005 to work with ST Microelectronics in Ottawa. He has received two Best Paper Awards and several honorary mentions from international conferences, as well as a national teaching award in Canada.
Summary
High-Speed Serial Interface (HSSI) devices have become widespread in communications, from the embedded to high-performance computing systems, and from on-chip to a wide haul. Testing of HSSIs has been a challenging topic because of signal integrity issues, long test time and the need of expensive instruments. Accelerating Test, Validation and Debug of High Speed Serial Interfaces provides innovative test and debug approaches and detailed instructions on how to arrive to practical test of modern high-speed interfaces.
Accelerating Test, Validation and Debug of High Speed Serial Interfaces first proposes a new algorithm that enables us to perform receiver test more than 1000 times faster. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms, while the test usually takes seconds. The book also presents and external loopback-based testing scheme, where and FPGA-based BER tester and a novel jitter injection technique are proposed. These schemes can be applied to validate, test and debug HSSIs with data rate up to 12.5Gbps at a lower test cost than pure ATE solutions. In addition, the book introduces an efficieng scheme to implement high performance Gaussian noise generators, suitable for evaluating BER performance under noise conditions.
