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Cutting-edge Design for Manufacturability Techniques for Nanoscale CMOS VLSI Circuits
Covering defect analysis, equipment, and lithographic control evaluations, this book offers a holistic approach for VLSI circuit designers to evaluate and analyze IC circuit designs from the manufacturability point of view. This practical guide is ideal for design engineers, managers, students, and academics interested in understanding the sources of semiconductor chip failures and how these problems can be mitigated through design.
List of contents
1. Introduction
1.1. Current trends in CMOS VLSI Design
1.2. What is Design for Manufacturability
1.2.1. Why is its important
1.2.2. Economics of DFM
1.3. What is Design for Reliability
1.3.1. Traditional definition
1.3.2. Expanded definition
1.3.3. Why is this an important topic
1.4. Summary
2. Semiconductor Manufacturing
2.1. Introduction
2.2. Fabrication Process
2.3. Lithography Simulation
2.3.1. Fraunhofer Diffraction
2.3.2. Aerial Image Formation
2.4. Importance of Aerial imaging simulation
2.5. Inverse Lithography Simulation
2.6. Summary
3. Lithographic Process Variability
3.1. Introduction
3.2. Variability in Gate Length & Width
3.3. Threshold Voltage Variability
3.4. Metal CMP
3.5. Interconnect linewidth variation
3.6. Interconnect LER
3.7. Summary
4. Lithographic Control
4.1. Introduction
4.2. Physical design rules check
4.2.1. The end of Boolean Rule-based checks
4.2.2. Model-based design rule checks
4.2.3. Cost vs accuracy of model-based checks
4.3. Resolution Enhancement Techniques (RET)
4.3.1. Proximity Correction & SRAFs
4.3.2. Phase shift Masking
4.3.3. Off-Axis Illumination
About the author
Dr. Sandip Kundu is a professor in the Electrical and Computer Engineering Department at the University of Massachusetts at Amherst, specializing in semiconductor and lithographic manufacturing.
Dr. Aswin Sreedhar is a research assistant at the Electrical and Computer Engineering Department at the University of Massachusetts.
Summary
Cutting-edge Design for Manufacturability Techniques for Nanoscale CMOS VLSI Circuits
