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Informationen zum Autor Eugene John, Juan Rubio Klappentext The demands of emerging software applications can be met only with unique chips and systems. This book addresses several systems and chips that provide new approaches to designing future computing and communication systems. The text presents the TRIPS processor architecture and microarchitecture! the CELL processor from IBM STI! and the continuation based Fuce multi-threading processor. Extended analog computers; Ravenscar! hardware-implemented run-time kernel with delay queues; formal state models and their simulations; and example graphics applications that require enormous computing power are also included to complete the comprehensive coverage in this book. Zusammenfassung The demands of software applications can be met only with unique chips and systems. This book addresses several systems and chips that provide fresh approaches to designing future computing and communication systems. It presents the TRIPS processor architecture and microarchitecture, and the CELL processor from IBM STI. Inhaltsverzeichnis Aspects of the Cell Processor. TRIPS: A Unique ISA and Microarchitecture for Concurrency. Visualization by Subdivision: Two Applications for Future Graphics Platforms. A High Throughput Self-Timed FPGA Core Architecture. Evaluation of Delay Queues for a Ravenscar Hardware Kernel. Forward Error Correction for On-chip Interconnection Networks. Analysis of Wavefront Algorithms on Large-scale Two-level Heterogeneous Processing Systems. Measurement Based Power Phase Analysis of a Commercial Workload. Microarchitectural Characteristics and Implications of Alignment of Multiple Bioinformatics Sequences. Extended Analog Computers: A Unifying Paradigm for VLSI, Plastic, and Colloidal Computing Systems. Integrated High Performance Security in a x86 Processor. Alleviating Thermal Constraints while Maintaining Performance via Silicon-based On-Chip Optical Interconnects. Power Management in RAID Server Disk System Using Multiple Idle States. Micro-threaded Row and Column Operations in a DRAM Core. A processor with Dual Thread Execution Models....
