Fr. 92.00

Applied Reconfigurable Computing. Architectures, Tools, and Applications - 21st International Symposium, ARC 2025, Seville, Spain, April 9-11, 2025, Proceedings

English · Paperback / Softback

Shipping usually within 6 to 7 weeks

Description

Read more

This book constitutes the proceedings of the 21st International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications, ARC 2025, held in Seville, Spain, during April 9 11, 2025.
The 12 full papers presented in this book together with 1 short paper from the technical program were carefully reviewed and selected from 40 submissions.
ARC 2025 covers a wide range of topics, including hardware acceleration, security and fault tolerance, energy-efficient architectures, and emerging applications in artificial intelligence and high-performance computing. The symposium fostered collaboration and pushed the boundaries of state-of-the-art research.

List of contents

First Twenty Years of the International Symposium on Applied Reconfigurable Computing (ARC): a Selection of Papers.- HT-NoC: Reconfigurable High Throughput Network-on-Chip for AI Dataflow Accelerators.- An MLIR-based Compilation Framework for CGRA Application Deployment.- Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA.- RePAIR: Reconfigurable Platform for AI Resilience within RISC-V Ecosystem.- ROBoost: A Study of FPGA Logic-Based Power-Wasting Primitives.- FLARE: An FPGA-based Universal Large Flow Detection Engine.- Out-of-the-Box Performance of FPGAs for ML Workloads using Vitis AI.- A Heterogeneous Embedded Platform for AI-based Protocol Identification.- Counting Heavy Items in Filtered Data Streams Using an HLS-Generated FPGA Kernel.- Ultra-low Latency and Extreme Throughput Echo State Neural Networks on FPGA.- A Reconfigurable Stream-Based FPGA Accelerator for Bayesian Confidence Propagation Neural Networks.- Real-Time Multi-Object Tracking using YOLOv8 and SORT on a SoC FPGA.- Dynamic Function Exchange in FPGA to Redefine RISC-V Multicore Architectures at Runtime.

Product details

Authors Dirk Stroobandt
Assisted by Ángel Barriga Barros (Editor), Piedad Brox Jimenez (Editor), Piedad Brox Jiménez (Editor), Piedad Brox Jimenez et al (Editor), Roberto Giorgi (Editor), Mirjana Stojilovic (Editor), Mirjana Stojilović (Editor), Dirk Stroobandt (Editor), Dirk Stroobandt et al (Editor)
Publisher Springer, Berlin
 
Languages English
Product format Paperback / Softback
Released 08.06.2025
 
EAN 9783031879944
ISBN 978-3-0-3187994-4
No. of pages 246
Dimensions 155 mm x 14 mm x 235 mm
Weight 400 g
Illustrations XIV, 246 p. 100 illus., 81 illus. in color.
Series Lecture Notes in Computer Science
Subjects Natural sciences, medicine, IT, technology > IT, data processing > Hardware

Hardware, Software Engineering, computer hardware, Information systems, Computer Engineering and Networks, Applied computing, Electronic Design Automation, parallel architectures, Design methods and tools, FPGA design, Reconfigurable architectures

Customer reviews

No reviews have been written for this item yet. Write the first review and be helpful to other users when they decide on a purchase.

Write a review

Thumbs up or thumbs down? Write your own review.

For messages to CeDe.ch please use the contact form.

The input fields marked * are obligatory

By submitting this form you agree to our data privacy statement.