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Zusatztext "Cavanagh has provided readers with a very large work on the topics of addition! subtraction! multiplication! and division. ? The student who completes a course based on this work will have achieved a great deal. Summing Up: Recommended."-CHOICE! June 2010 Informationen zum Autor Joseph Cavanagh is an adjunct professor in the computer engineering department at Santa Clara University in California. Klappentext This book presents the design of computer arithmetic circuits for four arithmetic operations using three number representations. The circuits are designed using algorithms or traditional design techniques and implemented using Verilog hardware description language (HDL) in the SILOS simulation environment. For each design method! the text illustrates the underling theory! examples of use! organization of the arithmetic function! logic design of the circuit! and Verilog HDL implementation. Verilog projects! including the design and test bench modules! as well as outputs and waveforms obtained from the simulator! illustrate the complete functional operation. Zusammenfassung Verilog Hardware Description Language (HDL) is the state-of-the-art method for designing digital and computer systems. This book details the steps needed to master computer arithmetic for fixed-point, decimal, and floating-point number representations for all primary operations. It is suitable for electrical and computer engineers. Inhaltsverzeichnis Chapter 1 Number Systems and Number RepresentationsNumber Systems Number RepresentationsChapter 2 Logic Design Fundamentals Boolean AlgebraMinimization TechniquesCombinational LogicSequential LogicChapter 3 Introduction to Verilog HDLBuilt-In PrimitivesUser-Defined PrimitivesDataflow Modeling Behavioral ModelingStructural ModelingChapter 4 Fixed-Point AdditionRipple-Carry AdditionCarry Lookahead AdditionCarry-Save AdditionMemory-Based AdditionCarry-Select AdditionSerial AdditionChapter 5 Fixed-Point Subtraction Twos Complement SubtractionRipple-Carry SubtractionCarry Lookahead Addition/SubtractionBehavioral Addition/SubtractionChapter 6 Fixed-Point MultiplicationSequential Add-Shift MultiplicationBooth Algorithm MultiplicationBit-Pair Recoding MultiplicationArray MultiplicationTable Lookup MultiplicationMemory-Based MultiplicationMultiple-Operand MultiplicationChapter 7 Fixed-Point DivisionSequential Shift-Add/Subtract Restoring DivisionSequential Shift-Add/Subtract Nonrestoring DivisionSRT DivisionMultiplicative DivisionArray DivisionChapter 8 Decimal AdditionAddition With Sum Correction Addition Using MultiplexersAddition With Memory-Based CorrectionAddition With Biased AugendChapter 9 Decimal SubtractionSubtraction ExamplesTwo-Decade Addition/Subtraction Unit for A+B and A-BTwo-Decade Addition/Subtraction Unit for A+B! A-B! and B-AChapter 10 Decimal MultiplicationBinary-to-BCD ConversionMultiplication Using Behavioral ModelingMultiplication Using Structural ModelingMultiplication Using MemoryMultiplication Using Table LookupChapter 11 Decimal DivisionRestoring Division - Version 1Restoring Division - Version 2Division Using Table LookupChapter 12 Floating-Point AdditionFloating-Point FormatBiased ExponentsFloating-Point AdditionOverflow and UnderflowGeneral Floating-Point OrganizationVerilog HDL ImplementationChapter 13 Floating-Point SubtractionNumerical ExamplesFlowchartsVerilog HDL ImplementationsChapter 14 Floating-Point MultiplicationDouble BiasFlowchartsNumerical ExamplesVerilog HDL Implementations Chapter 15 Floating-Point DivisionZero BiasExponent Overflow/UnderflowFlowchartsNumerical ExamplesChapter 16 Additional Floating-Point TopicsRounding MethodsGuard BitsVerilog HDL Implementations Chapter 17 Additional Topics in Computer ArithmeticResidue Checking Parity-Checked Shift Register...
