Fr. 195.00

Design of Cost-Efficient Interconnect Processing Units - Spidergon Stnoc

English · Hardback

New edition in preparation, currently unavailable

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Informationen zum Autor Marcello Coppola (STMicroelectronics, Grenoble, France) (Author) , Miltos D. Grammatikakis (ISD SA, Heraklion, Greece) (Author) , Riccardo Locatelli (STMicroelectronics, Grenoble Cedex, France) (Author) , Giuseppe Maruccia (STMicroelectronics, Grenoble, France) (Author) , Lorenzo Pieralisi (STMicroelectronics, Grenoble, France) (Author) Klappentext Written by leading experts in the field! Design of Cost-Efficient Interconnect Processing Units: "Spidergon STNoC" comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC)! in particular network-on-chip (NoC) design. Incorporating simple methods with easy-to-understand examples! this book considers a wealth of important theoretical and practical topics! such as technological deep sub-micron effects! generic NoC components! topological properties! embeddings of common communication patterns! and system-level design. A complementary CD-ROM features a practical NoC training approach based on the award-winning OCCN environment. Zusammenfassung Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-on-chip (NoC) design. Inhaltsverzeichnis Towards Multicores: Technology and Software Complexity. On-Chip Bus vs Network-on-Chip. NoC Topology. The Spidergon STNoC. SoC and NoC Design Methodology and Tools. Conclusions and Future Work.

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