Read more
Informationen zum Autor Praveen K. Murthy, Shuvra S. Bhattacharyya Klappentext Memory Management for Synthesis of DSP Software focuses on techniques for minimizing memory requirements during the synthesis of software from dataflow representations of DSP systems. This book reviews research for compiling synchronous dataflow specifications. Building on the formal foundation of synchronous dataflow-based software synthesis! it discusses recently developed techniques along with underlying theories that optimize memory consumption during compilation of synchronous dataflow specifications. It also describes buffer sharing models and techniques as well as addresses the DSA problem and its various solutions. This text is ideal for electrical and computer engineers. Zusammenfassung Focuses on techniques for minimizing memory requirements during the synthesis of software from dataflow representations of DSP systems. This book reviews research for compiling synchronous dataflow specifications. It describes buffer sharing models and techniques as well as addresses the DSA problem and its various solutions. Inhaltsverzeichnis INTRODUCTIONElectronic Embedded SystemsDigital Signal Processing SystemsActor-Oriented DesignDataflow MoCs for DSP SystemsSynthesis Techniques in AOPEsAdvances in Compilers for DSPsOther Related Work-Nested Loop SchedulingNOTATION AND BACKGROUNDGraph TerminologySynchronous DataflowSynthesis from SDF GraphsScheduling Problems for SDF GraphsConstructing Memory-Efficient Loop StructuresScheduling for Other MetricsOther Topics: HolesSummaryLIFETIME ANALYSISIntroductionThe Shared Buffer ModelCreating the Interval Instances from a SASConclusionDYNAMIC STORAGE ALLOCATIONSome NotationHeuristic for DSAComputing the Maximum Clique WeightExperimental ResultsApproximation AlgorithmsTHE CBP PARAMETERRelated WorkIntroduction to Buffer MergingThe CBP ParameterMultirate FIR FiltersChopAutocorrelationCBP TablesSummary of DerivationsConclusionBUFFER SHARING VIA MERGING TECHNIQUESMerging an Input/Output Buffer PairMerging a Chain of BuffersA Heuristic for Merged Cost-Optimal SASConclusionBUFFER MERGING ALGORITHMSAcyclic GraphsExperimental ResultsConclusionBEYOND SINGLE APPEARANCE SCHEDULESRecursive Decomposition of a Two-Actor SDF GraphExtension to Arbitrary SASCD-DAT ExampleExperimental ResultsConclusionCONCLUSIONRegularityFixed-Point OptimizationsReconfigurable SystemsGrand ChallengeREFERENCESINDEX ...
