A Pipelined Multi-Core Machine with Operating System Support - Hardware Implementation and Correctness Proof

This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:

- MIPS instruction set architecture (ISA) for application and for system programming

- cache coherent memory system
- store buffers in front of the data caches
- interrupts and exceptions
- memory management units (MMUs)
- pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
- local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
- I/O-interrupt controller and a disk
 

List of contents

Introductory material.- on hierarchical hardware design.- hardware library.- basic processor design.- pipelining.- cache memory systems.- interrupt mechanism.- self modification, instruction buffer and nondeterministic ISA.- memory management units.- store buffers.- multi-core processors.- advanced programmable interrupt controllers (APICs).- adding a disk.- I/O apic.

Product details

• Authors: Petr Lutsyk, Petro Lutsyk, Jona Oberhauser, Jonas Oberhauser, Wolfgang J Paul, Wolfgang J. Paul
• Publisher: Springer, Berlin
• Languages: English
• Product format: Paperback / Softback
• Released: 01.05.2020
• EAN: 9783030432423
• ISBN: 978-3-0-3043242-3
• No. of pages: 628
• Dimensions: 157 mm x 35 mm x 235 mm
• Weight: 961 g
• Illustrations: XV, 628 p. 1 illus.
• Series: Lecture Notes in Computer Science; Theoretical Computer Science and General Issues
• Subject: Natural sciences, medicine, IT, technology > IT, data processing > IT