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This book describes methods to address wearout/aging degradations in electronic chips and systems, caused by several physical mechanisms at the device level. The authors introduce a novel technique called accelerated active self-healing, which fixes wearout issues by enabling accelerated recovery. Coverage includes recovery theory, experimental results, implementations and applications, across multiple nodes ranging from planar, FD-SOI to FinFET, based on both foundry provided models and predictive models.
- Presents novel techniques, tested with experiments on real hardware;
- Discusses circuit and system level wearout recovery implementations, many of these designs are portable and friendly to the standard design flow;
- Provides circuit-architecture-system infrastructures that enable the accelerated self-healing for future resilient systems;
- Discusses wearout issues at both transistor and interconnect level, providing solutions that apply to both;
- Includes coverage of resilient aspects of emerging applications such as IoT.
List of contents
Introduction to Wearout.- Accelerated Self-Healing Techniques for BTI Wearout.- Accelerating and Activating Recovery for EM Wearout.- Circuit Techniques for Accelerated and Active Recovery.- Accelerated Self-Healing as a Key Design Knob for Cross-Layer Resilience.- Design and Aging Challenges in FinFET Circuits and Internet of Things (IoT) Applications.- Future Directions in Self-Healing.
About the author
Xinfei Guo is a Design Engineer in Semiconductor industry in US. He received his Ph.D. degree in Computer Engineering from the University of Virginia in May 2018. He also held a M.S. degree in Electrical and Computer Engineering from the University of Florida, Gainesville, FL, in 2012 and a B.S. degree in Microelectronics from Xidian University, Xi’an, China, in 2010. He has broad interests in digital circuit and microarchitectures. His research focused on Reliability (Wearout and Accelerated Recovery Techniques), Cross-layer power and reliability co-design methodology, Low-power and Energy-efficient digital design. He is a student member of the IEEE and ACM, and a recipient of the 2017 IEEE Circuits and Systems (CAS) Pre-Doctoral Scholarship. He also received the Best Paper Awards at SRC TECHCON 2017 and SELSE 2017, and received Louis T. Radar Graduate Research Award from ECE department and A. Richard Newton Young Student Fellowship from DAC 2013. He has published and co-authored more than 20 peer-reviewed papers and has served as an active reviewer for various IEEE/ACM conferences and journals, such as DAC, ISCAS, ICCD, ISVLSI, ICCAD, TCAS I and II, TVLSI, TCAD, D & T, etc. He is also a Featured Reviewer for ACM Computing Reviews and served as the conference committee for various conferences such as ISVLSI, NOCs, ASAP, PRIME, etc.
Mircea R. Stan received the Ph.D. (1996) and the M.S. (1994) degrees in Electrical and Computer Engineering from the University of Massachusetts at Amherst and the Diploma (1984) in Electronics and Communications from Politehnica University in Bucharest, Romania. Since 1996 he has been with the Charles L. Brown Department of Electrical and Computer Engineering at the University of Virginia, where he is now a professor. Professor Stan is teaching and doing research in the areas of high-performance low-power VLSI, temperature-aware circuits and architecture, embedded systems, spintronics, and nanoelectronics. He leads the High-Performance Low-Power (HPLP) lab and is a co-director of the Center for Automata Processing (CAP) and an assistant director of Center for Research in Intelligent Storage and Processing in Memory (CRISP). He has more than eight years of industrial experience, has been a visiting faculty at UC Berkeley in 2004-2005, at IBM in 2000, and at Intel in 2002 and 1999. He has received the NSF CAREER award in 1997 and was a co-author on best paper awards at SELSE 2017, ISQED 2008, GLSVLSI 2006, ISCA 2003 and SHAMAN 2002. He gave conference keynotes at SOCC 2016, CNNA 2014, WoNDP 2015 and iNIS 2015. He was the chair of the VSA-TC of IEEE CAS in 2005-2007, general chair for ISLPED 2006 and for GLSVLSI 2004, technical program chair for SOCC 2018, ISVLSI 2017, NanoNets 2007 and ISLPED 2005, and on technical committees for numerous conferences. He is a Senior Editor for the IEEE Transactions on Nanotechnology and an AE for IEEE Design & Test since 2014, and was an AE for the IEEE TNano in 2012-2014, IEEE TCAS I in 2004-2008 and for the IEEE TVLSI in 2001-2003. He was Guest Editor for the IEEE Computer special issue on Power-Aware Computing in December 2003 and a Distinguished Lecturer for the IEEE Circuits and Systems (CAS) Society in 2012-2013 and 2004-2005, and for the Solid-State Circuits Society (SSCS) in 2007-2008. Prof. Stan is a fellow of the IEEE, a member of ACM, and of Eta Kappa Nu, Phi Kappa Phi and Sigma Xi. His h-index is 49 and his i10-index is 124.
Summary
This book describes methods to address wearout/aging degradations in electronic chips and systems, caused by several physical mechanisms at the device level. The authors introduce a novel technique called accelerated active self-healing, which fixes wearout issues by enabling accelerated recovery. Coverage includes recovery theory, experimental results, implementations and applications, across multiple nodes ranging from planar, FD-SOI to FinFET, based on both foundry provided models and predictive models.
- Presents novel techniques, tested with experiments on real hardware;
- Discusses circuit and system level wearout recovery implementations, many of these designs are portable and friendly to the standard design flow;
- Provides circuit-architecture-system infrastructures that enable the accelerated self-healing for future resilient systems;
- Discusses wearout issues at both transistor and interconnect level, providing solutions that apply to both;
- Includes coverage of resilient aspects of emerging applications such as IoT.
