Fr. 135.00

Analysis and Design of Networks-on-Chip Under High Process Variation

English · Paperback / Softback

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Description

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This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

List of contents

Introduction.- Network On Chip Aspects.- Interconnection.- Process Variation.- Synchronous And Asynchronous NoC Design Under High Process Variation.- Novel Routing Algorithm.- Simulation Results.- Conclusions.

About the author

Magdy Ali El-Moursy is an Associate Professor in the Microelectronics Department of the Electronics Research Institute, Cairo, Egypt and Staff Engineer at Design Creation and Synthesis Division of Mentor Graphics Corporation, Cairo, Egypt.

Summary

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

Product details

Authors Magdy Al El-Moursy, Magdy Ali El-Moursy, Raba Ezz-Eldin, Rabab Ezz-Eldin, Hesha Hamed, Hesham F. A. Hamed
Publisher Springer, Berlin
 
Languages English
Product format Paperback / Softback
Released 01.01.2019
 
EAN 9783319798370
ISBN 978-3-31-979837-0
No. of pages 141
Dimensions 153 mm x 236 mm x 9 mm
Weight 261 g
Illustrations XXI, 141 p. 84 illus., 34 illus. in color.
Subjects Natural sciences, medicine, IT, technology > Technology > Electronics, electrical engineering, communications engineering

B, Microprocessors, engineering, Circuits and Systems, Electronics, Microelectronics, Electronics and Microelectronics, Instrumentation, Electronics engineering, Electronic circuits, Electronic Circuits and Systems, Computer architecture & logic design, Processor Architectures

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