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Informationen zum Autor R. JACOB (JAKE) BAKER, PHD, is an engineer, educator, and inventor. He has more than twenty years of engineering experience and holds more than 200 granted or pending patents in integrated circuit design. Jake is the author of several circuit design books for Wiley-IEEE Press. In 2007, he received the Hewlett-Packard Frederick Emmons Terman Award. Klappentext A revised guide to the theory and implementation of CMOS analog and digital IC design The fourth edition of CMOS: Circuit Design, Layout, and Simulation is an updated guide to the practical design of both analog and digital integrated circuits. The author--a noted expert on the topic--offers a contemporary review of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and switching power supplies. CMOS includes discussions that detail the trade-offs and considerations when designing at the transistor-level. The companion website contains numerous examples for many computer-aided design (CAD) tools. Using the website enables readers to recreate, modify, or simulate the design examples presented throughout the book. In addition, the author includes hundreds of end-of-chapter problems to enhance understanding of the content presented. This newly revised edition: Provides in-depth coverage of both analog and digital transistor-level design techniques Discusses the design of phase- and delay-locked loops, mixed-signal circuits, data converters, and circuit noise Explores real-world process parameters, design rules, and layout examples Contains a new chapter on Power Electronics Written for students in electrical and computer engineering and professionals in the field, the fourth edition of CMOS: Circuit Design, Layout, and Simulation is a practical guide to understanding analog and digital transistor-level design theory and techniques. Inhaltsverzeichnis Preface xxxiii Chapter 1 Introduction to CMOS Design 1 1.1 The CMOS IC Design Process 1 1.1.1 Fabrication 2 1.2 CMOS Background 5 1.3 An Introduction to SPICE 8 Chapter 2 The Well 31 2.1 Patterning 32 2.1.1 Patterning the N-well 35 2.2 Laying Out the N-well 35 2.2.1 Design Rules for the N-well 36 2.3 Resistance Calculation 36 2.3.1 The N-well Resistor 38 2.4 The N-well/Substrate Diode 39 2.4.1 A Brief Introduction to PN Junction Physics 39 2.4.2 Depletion Layer Capacitance 42 2.4.3 Storage or Diffusion Capacitance 45 2.4.4 SPICE Modeling 46 2.5 The RC Delay through the N-well 48 2.6 Twin Well Processes 51 Chapter 3 The Metal Layers 59 3.1 The Bonding Pad 59 3.1.1 Laying Out the Pad I 60 3.2 Design and Layout Using the Metal Layers 63 3.2.1 Metal1 and Via1 63 3.2.2 Parasitics Associated with the Metal Layers 63 3.2.3 Current-Carrying Limitations 67 3.2.4 Design Rules for the Metal Layers 68 3.2.5 Contact Resistance 69 3.3 Crosstalk and Ground Bounce 70 3.3.1 Crosstalk 71 3.3.2 Ground Bounce 72 3.4 Layout Examples 74 3.4.1 Laying Out the Pad II 74 3.4.2 Laying Out Metal Test Structures 76 Chapter 4 The Active and Poly Layers 83 4.1 Layout Using the Active and Poly Layers 83 4.1.1 Process Flow 90 4.2 Connecting Wires to Poly and Active 93 4.3 Electrostatic Discharge (ESD) Protection 99 Chapter 5 Resistors, Capacitors, MOSFETs 107 5.1 Resistors 107 5.2 Capacitors 115 5.3 MOSFETs 118 5.4 Layout Examples 125 Chapter 6 MOSFET Operation 135 6.1 MOSFET Capacitance Overview/Review 136 6.2 The Threshold Voltage 139 6.3 IV Characteristics o...
