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This book addresses Software-Defined Radio (SDR) baseband processing from the computer architecture point of view, providing a detailed exploration of different computing platforms by classifying different approaches, highlighting the common features related to SDR requirements and by showing pros and cons of the proposed solutions. It covers architectures exploiting parallelism by extending single-processor environment (such as VLIW, SIMD, TTA approaches), multi-core platforms distributing the computation to either a homogeneous array or a set of specialized heterogeneous processors, and architectures exploiting fine-grained, coarse-grained, or hybrid reconfigurability.
List of contents
Chapter1. The Evolution of Software Defined Radio - An Introduction.- Part I: Architectures, Designs and Implementations.- Chapter2. Design Transformation from a Single-Core to a Multi-Core Architecture targeting Massively-Parallel Signal Processing Algorithms.- Chapter3. The CoreVA-MPSoC - A Multiprocessor Platform for Software-Defined Radio.- Chapter4. Design and Implementation of IEEE 802.11a/g Receiver Blocks on a Coarse-Grained Reconfigurable Array.- Chapter5. Reconfigurable Multiprocessor Systems-on-Chip.- Chapter6. NineSilica: A Homogeneous MPSoC approach for SDR platforms.- Part II: Software-based Radio Cognition and Implementation Tools.- Chapter7. Application of the Scalable Communications Core as an SDR Baseband.- Chapter8. HW/SW Co-Design Toolset for Customization of Exposed Datapath Processors.- Chapter9. FPGA-based Cognitive Radio Platform with Reconfigurable Front-End and Antenna.- Chapter10. Synchronization in NC-OFDM-Based CR Platforms.- Chapter11. Towards Adaptive Cryptography and Security with Software Defined Platforms.- Chapter12. The Future of Software-Defined Radio-Recommendations.
About the author
Dr. Waqar Hussain is currently a Senior Research Scientist at the Department of Electronics and Communications Engineering, Tampere University of Technology, Finland. He has been a Visiting Scientist at the Department of Computer Science, University of Chicago, IL, USA and also at the Chair for Integrated Signal Processing Systems, Rheinisch-Westfaelische Technische Hochschule (RWTH), Aachen, Germany. His research interests include design and development of homogeneous and heterogeneous multicore and manycore systems that are specialized for application specific, reconfigurable and general purpose processing. He is actively working on Accelerator-Rich Architectures and issues related to Communication Infrastructures e.g., Network-on-Chip in an effort to exploit the underutilized part of the chip known as Dark Silicon. Dr. Waqar Hussain has a doctorate degree in Electronics Engineering from Tampere University of Technology, Finland.
Jari Nurmiis a professor at the Department of Electronics and Communications Engineering in Tampere University of Technology (TUT). He has held various research, education and management positions at TUT and in the industry since 1987. He got a D.Sc.(Tech) degree from TUT in 1994. His current research interests include System-on-Chip integration, on-chip communication, embedded and application-specific processor architectures, and circuit and system design and implementation for digital communication, positioning and DSP. He is leading a group of about 15 researchers and research associates at TUT.
Jouni Isoaho is a Professor in the Department of Applied Physics, Laboratory of Electronics and Information Technology at the University of Turku, Finland. His research focuses on Low power system design for DSP and telecom systems, VLSI system design methodologies, and Innovative radio architectures and design methodologies.
Fabio Garzia received his MSc degree in Electronics Engineer in March 2005 from the University of Bologna, Italy. After his graduation, he worked for a few months at ARCES Labs in Bologna, first as VLSI Layout Engineer then as Digital Designer. In 2006 he moved to Tampere, Finland, where he started his PhD studies. His PhD Thesis focused on the design of a coarse-grain reconfigurable accelerator at RTL level, the development of programming tools, design of SoC platforms based on this accelerator, implementation on FPGA and mapping of some applications on it. He received his Dr.Tech. (PhD) Degree in December 2009. From January 2010 to April 2011, he received a research grant for the development of a high-level compiler for the reconfigurable accelerator. In October 2011 he moved to Germany, where he joined the Navigation Group, Power-Efficient Systems Department at Fraunhofer IIS. His main activity regards the development of digital hardware and HW/SW interfaces for GNSS receivers targeting both ASIC and FPGA technologies. In May 2015 he received the title of Senior Engineer at Fraunhofer IIS.
Summary
This book addresses Software-Defined Radio (SDR) baseband processing from the computer architecture point of view, providing a detailed exploration of different computing platforms by classifying different approaches, highlighting the common features related to SDR requirements and by showing pros and cons of the proposed solutions. It covers architectures exploiting parallelism by extending single-processor environment (such as VLIW, SIMD, TTA approaches), multi-core platforms distributing the computation to either a homogeneous array or a set of specialized heterogeneous processors, and architectures exploiting fine-grained, coarse-grained, or hybrid reconfigurability.
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