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A detailed introduction to the design, modeling, and operation of junctionless field effect transistors (FETs), including advantages and limitations.
List of contents
1. Introduction; 2. Review on modeling junctionless FETs; 3. The EPFL charge-based model of junctionless field-effect transistors; 4. Model driven design - space of junctionless FETs; 5. Generalization of the charge based model: accounting for inversion layers; 6. Predicted performances of junctionless FETs; 7. Short channel effects in symmetric junctionless double-gate FETs; 8. Modeling AC operation in symmetric double-gate and nanowire JL FETs; 9. Modeling asymmetric operation of double-gate junctionless FETs; 10. Modeling noise behavior in junctionless FETs; 11. Carrier mobility extraction methodology in JL and inversion mode FETs; 12. Revisiting the Junction FET: a junctionless FET with an ¿ gate capacitance; 13. Modeling junctionless FET with interface traps targeting biosensor applications; Appendix A. Design - space of twin gate junctionless vertical slit FETs; Appendix B. Transient off-current in junctionless FETs; Appendix C. Derivatives of mobile charge density with respect to VGS and VDS; Appendix D. Global charge density at drain in depletion mode; Appendix E. Global charge density at drain in accumulation mode; Appendix F. The EPFL Junctionless MODEL ver.1.0.
About the author
Farzan Jazaeri is a Scientist at the Ecole Polytechnique Fédérale de Lausanne where his research interests focus on semiconductor devices and physics, and particularly the modeling and fabrication of field-effect transistors.Jean-Michel Sallese is a Senior Scientist at the Ecole Polytechnique Fédérale de Lausanne. He specialises in the analytical modeling of bulk and multigate field-effect transistors.
Summary
The first of its kind, this is a detailed introduction to this new and fast-developing field. It covers the design, modeling, and operation of junctionless field effect transistors (FETs), as well as advantages and limitations. It is Ideal for graduate students and researchers working in semiconductor nanotechnology.
