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Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base.
LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination.
The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r
egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers.
List of contents
1 Introduction.- 2 Background.- 3 Modeling UPF.- 4 Power Aware Standardization of Library.- 5 UPF Based Power Aware Dynamic Simulation.- 6 Power Aware Dynamic Simulation Coverage.- 7 UPF Based Power Aware Static Verification.- 8 References.
About the author
Progyna Khondkar is a low power design and verification expert and senior verification engineer at Mentor Graphics in the design verification technology division (DVT). He holds two patents and has numerous publications in power aware verification. He has strong focus on electronics, computer and information science education, research and teaching experiences in top level universities in Asia. He has worked for Hardware-Software design, development, integration, test and verification in the world class ASIC & Electronic Design Automation (EDA) companies for the last 15 years. He holds a PhD in Computer Science and is a senior member of IEEE. He also serves as a member of editorial board and reviewer of Journal of INFORMATION, IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, IEEE Transactions on Computers and Journal of VLSI Design and Verification (JVLSIDV).
Summary
Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base.
LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination.
The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r
egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers.
