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In DSP Architecture Design Essentials, authors Dejan Markovic and Robert W. Brodersen cover a key subject for the successful realization of DSP algorithms for communications, multimedia, and healthcare applications. The book addresses the need for DSP architecture design that maps advanced DSP algorithms to hardware in the most power- and area-efficient way.
The key feature of this text is a design methodology based on a high-level design model that leads to hardware implementation with minimum power and area. The methodology includes algorithm-level considerations such as automated word-length reduction and intrinsic data properties that can be leveraged to reduce hardware complexity. From a high-level data-flow graph model, an architecture exploration methodology based on linear programming is used to create an array of architectural solutions tailored to the underlying hardware technology.
The book is supplemented with online material: bibliography, design examples, CAD tutorials and custom software.
List of contents
Energy and Delay Models.- Circuit Optimization.- Architectural Techniques.- Architecture Flexibility.- Arithmetic for DSP.- CORDIC, Divider, Square Root.- Digital Filters.- Time-Frequency Analysis.- Data-Flow Graph Model.- Wordlength Optimization.- Architectural Optimization.- Simulink-Hardware Flow.- Multi-GHz Radio DSP.- Dedicated MHz-rate Decoders.- Flexible MHz-rate Decoder.- kHz-rate Neural Processors.- Brief Outlook.
Summary
In DSP Architecture Design Essentials, authors Dejan Marković and Robert W. Brodersen cover a key subject for the successful realization of DSP algorithms for communications, multimedia, and healthcare applications. The book addresses the need for DSP architecture design that maps advanced DSP algorithms to hardware in the most power- and area-efficient way.
The key feature of this text is a design methodology based on a high-level design model that leads to hardware implementation with minimum power and area. The methodology includes algorithm-level considerations such as automated word-length reduction and intrinsic data properties that can be leveraged to reduce hardware complexity. From a high-level data-flow graph model, an architecture exploration methodology based on linear programming is used to create an array of architectural solutions tailored to the underlying hardware technology.
The book is supplemented with online material: bibliography, design examples, CAD tutorials and custom software.
