Fr. 59.90

Cmos design of tree multiplier using low power vlsi and full adder

English · Paperback / Softback

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Description

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A modification to the Wallace reduction is presented that ensures that the delay is the same as for the conventional Wallace reduction. The modified reduction method greatly reduces the number of half adders; producing implementations with 80 percent fewer half adders than standard Wallace multipliers, with a very slight increase in the number of full adders.In case of CMOS, addition of a single input increases the device count by 2 and thus increases the propagation delay. New logic styles were developed to minimize the propagation delay and chip area.

About the author










Sneha DravyekarMtech in VLSI at RTMNUAssistant Professor at Om Polytechnic,UmrerIndia

Product details

Authors Sneha Dravyekar
Publisher Scholar's Press
 
Languages English
Product format Paperback / Softback
Released 21.02.2017
 
EAN 9783659845710
ISBN 978-3-659-84571-0
No. of pages 72
Subject Natural sciences, medicine, IT, technology > Technology > Electronics, electrical engineering, communications engineering

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