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As technology scaling enters into nanometer geometries, there is a significant increase in performance uncertainty of System-on-chip designs due to parametric variations. Process variability is posing an increasing challenge in timing analysis for designers. The traditional corner-based approach is not effective anymore and it will induce pessimism. Therefore, statistical timing analysis has become very important in overcoming the weakness of the traditional methods. By constructing statistical timing models for variations, chip performance and parametric yield will be more accurately predicted. In this work, variability aware statistical timing models of standard cells and system level interconnects are developed by using SPICE simulations, and statistical timing analysis flow and characterization automation are summarized.
About the author
Di Wang is a researcher at Microsoft Research. He received B.E. in computer science from Zhejiang University, M.S. in computer systems engineering from the Technical University of Denmark, and Ph.D. in computer science from Pennsylvania State University. His research work span the areas of computer systems, computer architecture and VLSI design.
