Low Power Networks-on-Chip

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

List of contents

Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSoCs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.

Summary

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

Product details

• Assisted by: Marcell Lajolo (Editor), Marcello Lajolo (Editor), Gianluca Palermo (Editor), Cristina Silvano (Editor)
• Publisher: Springer, Berlin
• Languages: English
• Product format: Paperback / Softback
• Released: 01.01.2014
• EAN: 9781489994370
• ISBN: 978-1-4899-9437-0
• No. of pages: 287
• Dimensions: 154 mm x 16 mm x 234 mm
• Weight: 474 g
• Illustrations: XIX, 287 p.
• Subjects: Natural sciences, medicine, IT, technology > Technology > Electronics, electrical engineering, communications engineering; B, Computer-Aided Design (CAD), engineering, Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design, Computer-aided engineering, Electronic circuits, Electronic Circuits and Systems