Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

List of contents

Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.

Summary

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

Product details

• Authors: Sumi Ahuja, Sumit Ahuja, Avinas Lakshminarayana, Avinash Lakshminarayana, Sand Shukla, Sandeep Kumar Shukla
• Publisher: Springer, Berlin
• Languages: English
• Product format: Paperback / Softback
• Released: 01.01.2014
• EAN: 9781489987808
• ISBN: 978-1-4899-8780-8
• No. of pages: 170
• Dimensions: 154 mm x 12 mm x 236 mm
• Weight: 302 g
• Illustrations: XXII, 170 p.
• Subjects: Natural sciences, medicine, IT, technology > Technology > Electronics, electrical engineering, communications engineering; B, Computer-Aided Design (CAD), engineering, Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design, Computer-aided engineering, Electronic circuits, Electronic Circuits and Systems