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Caches in Embedded Systems improve average case performance, but they are a source of unpredictability, especially in the worst case software timing analysis with the consideration of data caches. This is a critical problem in real-time systems, where tight Worst Case Execution Time (WCET) is required for their schedulability analysis. Few works have studied data cache impacts on the WCET of programs, but only for programs with no input-dependent data accesses. To provide an efficient and accurate analysis for input-dependent data accesses, we develop classified cache architecture and a WCET framework for the architecture. Our work classifies predictable and unpredictable accesses, then allocates them into predictable caches and unpredictable caches accordingly, and uses CME (Cache Miss Equations) and our reuse-distance-based algorithm for their timing analysis respectively. Compared with simulation, our analysis framework produces a very good WCET tightness, and our architecture creates almost no hardware overhead or performance degradation. In addition, we examine NP-completeness of WCET analysis. We also explore data allocation techniques to improve system performance.
About the author
After Bachelor in Computer Science from NEU, I did my Master in Computer Engineering from National University of Singapore. During which,I went to ETH Zurich to conduct research in distributed computing. After my Master, I worked at Motorola and then Gemalto as Software Engineer in Singapore.Now I work at Motorola Mobility in Chicago.
