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Informationen zum Autor David Culler led the Berkeley Network of Workstations (NOW) project, which sparked the current commercial revolution in high-performance clusters. Anoop Gupta co-led the Stanford DASH multiprocessor project, which developed the shared-memory technology increasingly used in commercial machines. Jaswinder Pal Singh led the development of the SPLASH and SPLASH-2 suites of parallel programs, which have defined the workloads and methodology used to drive decisions and evaluate trade-offs in shared- memory parallel architecture. Dr. Anoop Gupta is a Distinguished Scientist at Microsoft Research. He works on cross-disciplinary projects that have potential for large business or societal impact. His recent projects focus on areas of education, communication, collaboration, and natural user interfaces. Klappentext This book outlines a set of issues that are critical to all of parallel architecture--communication latency, communication bandwidth, and coordination of cooperative work (across modern designs). It describes the set of techniques available in hardware and in software to address each issues and explore how the various techniques interact.The most exciting development in parallel computer architecture is the convergence of traditionally disparate approaches on a common machine structure. This book explains the forces behind this convergence of shared-memory, message-passing, data parallel, and data-driven computing architectures. Inhaltsverzeichnis 1 Introduction 2 Parallel Programs 3 Programming for Performance 4 Workload-Driven Evaluation 5 Shared Memory Multiprocessors 6 Snoop-based Multiprocessor Design 7 Scalable Multiprocessors8 Directory-based Cache Coherence9 Hardware-Software Tradeoffs 10 Interconnection Network Design 11 Latency Tolerance 12 Future Directions APPENDIX A Parallel Benchmark Suites
List of contents
1 Introduction
2 Parallel Programs
3 Programming for Performance
4 Workload-Driven Evaluation
5 Shared Memory Multiprocessors
6 Snoop-based Multiprocessor Design
7 Scalable Multiprocessors
8 Directory-based Cache Coherence
9 Hardware-Software Tradeoffs
10 Interconnection Network Design
11 Latency Tolerance
12 Future Directions
APPENDIX A Parallel Benchmark Suites
