Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

List of contents

Introduction; Related work; Background; Statistical Regression Based Power Models; Statistical Regression Based Power Models for FPGAs; High Level Simulation Directed RTL Power Estimation; Applying Verification Collaterals for Accurate Power Estimation; Architectural Selection using High Level Synthesis; Power Reduction using High-Level Clock-gating; Model-Checking to exploit Sequential Clock-Gating; Power model to facilitate aggressive reduction; Coprocessor Design Space Exploration using High Level Synthesis.

Summary

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

Product details

• Authors: Sumi Ahuja, Sumit Ahuja, Avinas Lakshminarayana, Avinash Lakshminarayana, Sand Shukla, Sandeep Kumar Shukla
• Publisher: Springer, Berlin
• Languages: English
• Product format: Hardback
• Released: 01.11.2011
• EAN: 9781461408710
• ISBN: 978-1-4614-0871-0
• No. of pages: 170
• Weight: 472 g
• Illustrations: XXII, 170 p.
• Subject: Natural sciences, medicine, IT, technology > Technology > Electronics, electrical engineering, communications engineering