Fr. 70.00

Evaluation of State-of-the-Art Hardware Architectures for Fast Cone-Beam CT Reconstruction

English · Paperback / Softback

Shipping usually within 6 to 7 weeks

Description

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This book considers the field of computed tomography including a review of state-of-the-art reconstruction algorithms and a concise assessment of the most recent hardware architectures.

Holger Scherl introduces the reader to the reconstruction problem in computed tomography and its major scientific challenges that range from computational efficiency to the fulfillment of Tuy's sufficiency condition. The assessed hardware architectures include multi- and many-core systems, cell broadband engine architecture, graphics processing units, and field programmable gate arrays. The author focuses on the interplay between these recent hardware platforms and modern computed tomography reconstruction algorithms.

List of contents

Aus dem Inhalt:
Algorithms for Cone-Beam Image Reconstruction, Design and Implementation of a General Reconstruction Framework, Cell Broadband Engine Architecture, Standard Multi-Core Processors, Graphics Accelerator Boards, FPGA-Based Hardware, Performance Optimization of Selected Feldkamp Alternatives

About the author

Holger Scherl earned his doctoral degree at the Pattern Recognition Lab of the Department of Computer Science, University of Erlangen-Nuremberg, under the supervision of Professor Joachim Hornegger. He works at a major healthcare company where he is responsible for the research and development of a hardware-accelerated software-platform for image reconstruction in computed tomography.

Summary

This book considers the field of computed tomography including a review of state-of-the-art reconstruction algorithms and a concise assessment of the most recent hardware architectures.

Holger Scherl introduces the reader to the reconstruction problem in computed tomography and its major scientific challenges that range from computational efficiency to the fulfillment of Tuy's sufficiency condition. The assessed hardware architectures include multi- and many-core systems, cell broadband engine architecture, graphics processing units, and field programmable gate arrays. The author focuses on the interplay between these recent hardware platforms and modern computed tomography reconstruction algorithms.

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