Vertical 3d Memory Technologies

The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then performance can be increased, power reduced and cost contained. This book reviews for the electronics industry engineer, professional and student the critical areas of development for 3D vertical memory chips including: gate-all-around and junction-less nanowire memories, stacked thin film and double gate memories, terrabit vertical channel and vertical gate stacked NAND flash, large scale stacking of Resistance RAM cross-point arrays, and 2.5D/3D stacking of memory and processor chips with through-silicon-via connections now and remote links later.
 
Key features:
* Presents a review of the status and trends in 3-dimensional vertical memory chip technologies.
* Extensively reviews advanced vertical memory chip technology and development
* Explores technology process routes and 3D chip integration in a single reference

List of contents

Acknowledgments xv
 
1 Basic Memory Device Trends Toward the Vertical 1
 
1.1 Overview of 3D Vertical Memory Book 1
 
1.2 Moore's Law and Scaling 2
 
1.3 Early RAM 3D Memory 3
 
1.4 Early Nonvolatile Memories Evolve to 3D 13
 
1.5 3D Cross-Point Arrays with Resistance RAM 20
 
1.6 STT-MTJ Resistance Switches in 3D 21
 
1.7 The Role of Emerging Memories in 3D Vertical Memories 22
 
References 23
 
2 3D Memory Using Double-Gate, Folded, TFT, and Stacked Crystal Silicon 25
 
2.1 Introduction 25
 
2.2 FinFET--Early Vertical Memories 26
 
2.3 Double-Gate and Tri-Gate Flash 37
 
2.4 Thin-Film Transistor (TFT) Nonvolatile Memory with Polysilicon Channels 43
 
2.5 Double-Gate Vertical Channel Flash Memory with Engineered Tunnel Layer 49
 
2.6 Stacked Gated Twin-Bit (SGTB) CT Flash 55
 
2.7 Crystalline Silicon and Epitaxial Stacked Layers 56
 
References 69
 
3 Gate-All-Around (GAA) Nanowire for Vertical Memory 72
 
3.1 Overview of GAA Nanowire Memories 72
 
3.2 Single-Crystal Silicon GAA Nanowire CT Memories 72
 
3.3 Polysilicon GAA Nanowire CT Memories 82
 
3.4 Junctionless GAA CT Nanowire Memories 88
 
3.5 3D Stacked Horizontal Nanowire Single-Crystal Silicon Memory 95
 
3.6 Vertical Single-Crystal GAA CT Nanowire Flash Technology 103
 
3.7 Vertical Channel Polysilicon GAA CT Memory 107
 
3.8 Graphene Channel Nonvolatile Memory with Al2O3-HfOx-Al2O3 Storage Layer 115
 
3.9 Cost Analysis for 3D GAA NAND Flash Considering Channel Slope 116
 
References 117
 
4 Vertical NAND Flash 119
 
4.1 Overview of 3D Vertical NAND Trends 119
 
4.2 Vertical Channel (Pipe) CT NAND Flash Technology 124
 
4.3 3D FG NAND Flash Cell Arrays 146
 
4.4 3D Stacked NAND Flash with Lateral BL Layers and Vertical Gate 159
 
References 189
 
5 3D Cross-Point Array Memory 192
 
5.1 Overview of Cross-Point Array Memory 192
 
5.2 A Brief Background of Cross-Point Array Memories 193
 
5.3 Low-Resistance Interconnects for Cross-Point Arrays 203
 
5.4 Cross-Point Array Memories Without Cell Selectors 207
 
5.5 Examples of Selectorless Cross-Point Arrays 217
 
5.6 Unipolar Resistance RAMs with Diode Selectors in Cross-Point Arrays 227
 
5.7 Unipolar PCM with Two-Terminal Diodes for Cross-Point Array 238
 
5.8 Bipolar Resistance RAMS With Selector Devices in Cross-Point Arrays 246
 
5.9 Complementary Switching Devices and Arrays 256
 
5.10 Toward Manufacturable ReRAM Cells and Cross-point Arrays 267
 
5.11 STT Magnetic Tunnel Junction Resistance Switches in Cross-Point Array Architecture 269
 
References 271
 
6 3D Stacking of RAM-Processor Chips Using TSV 275
 
6.1 Overview of 3D Stacking of RAM-Processor Chips with TSV 275
 
6.2 Architecture and Design of TSV RAM-Processor Chips 280
 
6.3 Process and Fabrication of Vertical TSV for Memory and Logic 292
 
6.4 Process and Fabrication Issues of TSV 3D Stacking Technology 299
 
6.5 Fabrication of TSVs 301
 
6.6 Energy Efficiency Considerations of 3D Stacked Memory-Logic Chip Systems 306
 
6.7 Thermal Characterization Analysis and Modeling of RAM-Logic Stacks 314
 
6.8 Testing of 3D Stacked TSV System Chips 316
 
6.9 Reliability Considerations with 3D TSV RAM-Processor Chips 320
 
6.10 Reconfiguring Stacked TSV Memory Architectures for Improved Performance 326
 
6.11 Stacking Memories Using Noncontact Connections with Inductive Coupling 333
 
References 340
&nb

About the author

Dr Betty Prince has over 30 years' experience in the semiconductor industry having worked with Texas Instruments, N.V. Philips, Motorola, R.C.A., and Fairchild and is currently CEO of Memory Strategies International. She has authored four books and served from 1991-1994 on the Technical Advisory Board of IEEE Spectrum magazine. She is a Senior Life Member of the IEEE and served as an IEEE SSCS Distinguished Lecturer and on the Program Committee of the IEEE Custom Integrated Circuit conference. She was founder of the JEDEC JC-16 Interface Standards Committee and was active for many years on the JC-42 Memory Committee where she was co-chair of the SRAM standards group. She has been U.S. representative to the IEC SC47A WG3 Memory Standards Committee. Dr Prince has served on the Technical Advisory Board of several memory companies and has been on the Board of Directors of Mosaid Technologies. She holds patents in the memory, processor and interface areas and has degrees in Physics, Math, and Finance with doctoral dissertation in fractal modeling.

Summary

The large scale integration and planar scaling of individual system chips is reaching an expensive limit.

Report

"In summary, Betty Prince has produced a piece of work that is timely and will undoubtedly become a classic text for 3D memory technologies." (3dincites.com, 30 September 2014)
 
"As the semiconductor memory industry moves to the third dimension a plethora of competing technologies has arisen each claiming to be the logical, lucrative successor to existing two dimensional versions. The very breadth of these new technologies can be confusing even to experienced industry professionals. Dr Prince's book appears at the right time to remove this confusion by explaining each technology's structure, function and potential advantages in a way that is accessible to both interested spectators and those working in the industry. It provides a welcome solid foundation to anyone interested in understanding the various technologies vying for success in this migration."
--Andrew Walker, Schiltron Corporation, USA
 
"This is a great review on the current state-of-the-art in the highly topical subject of vertical 3D memories. It comprises the challenges and current solutions of 3D memory integration with respective to different memory technologies. It is a highly valuable resource for researchers and engineers in the field of memory technology."
-- Dr. Stephan Menzel, Forschungszentrum Jülich (PGI-7), Germany ".... one to consider if you want to bring yourself up to speed on recent research behind today's and tomorrow's 3D memory technologies. The book provides capsule summaries of over 360 papers and articles from scholarly journals organized into sections of related technologies to provide an invaluable reference on a particular 3D technology. It's a useful tool for locating research covering any of the numerous 3D technologies that are now finding their way into early production."
-- Jim Handy, TheMemoryGuy.com, OBJECTIVE ANALYSIS Semiconductor Market Research, USA

Product details

• Authors: Prince, B Prince, Betty Prince, Betty (Motorola Inc. Prince
• Publisher: Wiley, John and Sons Ltd
• Languages: English
• Product format: Hardback
• Released: 26.09.2014
• EAN: 9781118760512
• ISBN: 978-1-118-76051-2
• No. of pages: 368
• Subject: Natural sciences, medicine, IT, technology > Technology > Electronics, electrical engineering, communications engineering