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Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results.
The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.
List of contents
1. Introduction.- 2. Introduction to PLLS.- 1 Introduction.- 2 PLL Basics.- 3 A Linear Model for PLLs.- 4 Conclusions.- 3. Phase Noise and Timing Jitter.- 1 Phase Noise.- 2 Timing Jitter.- 3 Phase Noise vs. Timing Jitter.- 4 Conclusions.- 4. Review of Existing VCO Phase Noise Models.- 1 Challenges in Oscillator Phase Noise Analysis.- 2 Leeson's Model.- 3 Razavi's Model.- 4 Hajimiri's Model.- 5. Universal Model for Ring Oscillator Phase Noise.- 1 Comparison and Analysis of Ring Oscillator Phase Noise.- 2 Modified Linear Model.- 3 Q-factor for Ring Oscillators.- 4 Noise Up-Conversion.- 5 Power Supply / Substrate Noise.- 6 Conclusions.- 6. New Ring VCO Design.- 1 Introduction.- 2 Phase Noise Overview.- 3 Circuit Design.- 4 Analysis of Circuits with Hysteresis.- 5 Simulation and Measurement.- 6 Conclusions.- 7. PLL Design Examples.- 1 PLL with Ring VCO.- 2 LC VCO.- 3 Simulation Results.- 4 Measurement Results.- 5 Conclusions.- 8. Conclusions.- 1 Research Contributions.- 2 Summary.
Summary
Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results.
The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.
