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Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
List of contents
NoC Design Methods.- Designing Crossbar Based Systems.- Netchip Tool Flow for NoC Design.- Designing Standard Topologies.- Designing Custom Topologies.- Supporting Multiple Applications.- Supporting Dynamic Application Patterns.- NoC Reliability Mechanisms.- Timing-Error Tolerant NoC Design.- Analysis of NoC Error Recovery Schemes.- Fault-Tolerant Route Generation.- NoC Support for Reliable On-Chip Memories.- Conclusions and Future Directions.
About the author
Dr. Srinivasan Murali is a co-founder and CTO of iNoCs and a research scientist at the Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland. He received the MS and PhD degrees in Electrical Engineering from Stanford University in 2007. His research interests include interconnect design for Systems on Chips, with particular emphasis on developing CAD tools and design methods for Networks on Chips. His interests also include thermal modeling and reliability of multi-core systems. He has been actively involved in several conferences (such as DATE, CODES-ISSS, NoC symposium, VLSI-SoC) as a program committee member/session chair and is a reviewer for many leading conferences and journals. He is a recipient of the EDAA outstanding dissertation award for 2007 for his work on interconnect architecture design. He received a best paper award at the DATE 2005 conference and a best paper nomination at the ICCAD 2006 conference.
One of his papers has also been selected as one of "The Most Influential Papers of 10 Years DATE". He has over 30 publications in leading conferences and journals in this field.
Summary
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
