Read more
Will nanoelectronic devices continue to scale according to Moore's law? At this moment, there is no easy answer since gate scaling is rapidly emerging as a serious roadblock for the evolution of CMOS technology. Channel engineering based on high-mobility semiconductor materials (e.g. strained Si, alternative orientation substrates, Ge or III-V compounds) could help overcome the obstacles since they offer performance enhancement. There are several concerns though. Do we know how to make complex engineered substrates (e.g. Germanium-on-Insulator)? Which are the best interface passivation methodologies and (high-k) gate dielectrics on Ge and III-V compounds? Can we process these materials in short channel transistors using flows, toolsets and know how similar to that in Si technology? How do these materials and devices behave at the nanoscale? The reader will get a clear view of what has been done so far, what is the state-of-the-art and which are the main challenges ahead before we come any close to a viable Ge and III-V MOS technology.
List of contents
Strained-Si CMOS Technology.- High Current Drivability MOSFET Fabricated on Si(110) Surface.- Advanced High-Mobility Semiconductor-on-Insulator Materials.- Passivation and Characterization of Germanium Surfaces.- Interface Engineering for High-? Ge MOSFETs.- Effect of Surface Nitridation on the Electrical Characteristics of Germanium High-?/Metal Gate Metal-Oxide-Semiconductor Devices.- Modeling of Growth of High-? Oxides on Semiconductors.- Physical, Chemical, and Electrical Characterization of High-? Dielectrics on Ge and GaAs.- Point Defects in Stacks of High-? Metal Oxides on Ge: Contrast with the Si Case.- High ? Gate Dielectrics for Compound Semiconductors.- Interface Properties of High-? Dielectrics on Germanium.- A Theoretical View on the Dielectric Properties of Crystalline and Amorphous High-? Materials and Films.- Germanium Nanodevices and Technology.- Opportunities and Challenges of Germanium Channel MOSFETs.- Germanium Deep-Submicron p-FET and n-FET Devices, Fabricated on Germanium-On-Insulator Substrates.- Processing and Characterization of III-V Compound Semiconductor MOSFETs Using Atomic Layer Deposited Gate Dielectrics.- Fabrication of MBE High-? MOSFETs in a Standard CMOS Flow.
About the author
Dr. Dimoulas obtained his Ph.D in Applied Physics from the University of Crete and the Foundation for Research & Technology-Hellas (FORTH), Greece in 1991 for his research on heteroepitaxial strain of III-V semiconductors grown on Si by MBE. He worked in the Microelectronics Research Group of FORTH until 1992. He was Human Capital & Mobility Fellow of the EU at the University of Groningen, Holland until 1994, a Research Fellow at the California Institute of Technology (CALTECH), Chemical Engineering, Pasadena USA until1996 and member of the Faculty at the University of Maryland at College Park (UMCP) USA, until February 1999. In addition, he has been visiting research scientist at NRL, Washington DC in 1992 and at IBM Zurich Research Laboratory, Switzerland in 2006. Since 1999, he is research director and head of the MBE laboratory at the Institute of Materials Science of the National Center for Scientific Research DEMOKRITOS, Athens, Greece. He is leading several European-funded projects in the areas of advanced microelectronic materials and devices. He has co-author more than 80 publications in international journals, archives and proceedings, and has also written book chapters. He has given 15 invited presentations during the last five years. He has been involved in the organization of several conferences and workshops either as the main organizer or as a member of advisory and program committees. Finally, he is reviewer in recognized International Journals and evaluator of research and development projects. His expertise includes MBE growth of Semiconductor and dielectric materials (high-k oxides), nanodevice processing by e-beam lithography and materials characterization and device electrical testing. His current interests focus on advanced high-k gate stacks for Ge and III-V MOS technology.
Summary
This book provides a comprehensive monograph on gate stacks in semiconductor technology. It covers the major latest developments and basics and will be useful as a reference work for researchers, engineers and graduate students alike. The reader will get a clear view of what has been done so far, what is the state-of-the-art and which are the main challenges ahead before we come any closer to a viable Ge and III-V MOS technology.
