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Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.
List of contents
Abstract.- Models and Tools.- Scratchpad Memory Optimizations.- Main Memory Optimizations.- Register File Optimization.- Summary.- Future Work.
About the author
Dr. Peter Marwedel received his PhD in Physics from the University of Kiel in 1974. He is one of the early researchers in high level synthesis, working on the MIMOLA system for a number of years. Dr. Marwedel is a professor at the University of Dortmund since 1989. He has served as the chairman of the computer science department, has played a leading role in establishing the Design, Automation and Test in Europe (DATE) conference and is the chairman of the Informatik Centrum Dortmund (ICD), a technology transfer centre.
Summary
Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.
