Fr. 135.00

Design of Interconnection Networks for Programmable Logic

English · Paperback / Softback

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Description

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Programmable Logic Devices (PLDs) have become the key implementation medium for the vast majority of digital circuits designed today. While the highest-volume devices are still built with full-fabrication rather than field programmability, the trend towards ever fewer ASICs and more FPGAs is clear. This makes the field of PLD architecture ever more important, as there is stronger demand for faster, smaller, cheaper and lower-power programmable logic. PLDs are 90% routing and 10% logic. This book focuses on that 90% that is the programmable routing: the manner in which the programmable wires are connected and the circuit design of the programmable switches themselves. Anyone seeking to understand the design of an FPGA needs to become lit erate in the complexities of programmable routing architecture. This book builds on the state-of-the-art of programmable interconnect by providing new methods of investigating and measuring interconnect structures, as well as new programmable switch basic circuits. The early portion of this book provides an excellent survey of interconnec tion structures and circuits as they exist today. Lemieux and Lewis then provide a new way to design sparse crossbars as they are used in PLDs, and show that the method works with an empirical validation. This is one of a few routing architecture works that employ analytical methods to deal with the routing archi tecture design. The analysis permits interesting insights not typically possible with the standard empirical approach.

List of contents

1. Introduction.- 2. Interconnection Networks.- 3. Models, Methodology and CAD Tools.- 4. Sparse Crossbar Design.- 5. Sparse Cluster Design.- 6. Routing Switch Circuit Design.- 7. Switch Block Design.- 8. Conclusions.- Appendices.- A Switch Blocks: Reduced Flexibility.- A.1 Introduction.- A.4 Results.- A.5 Summary.- B Switch Blocks: Diverse Design Instances.- C VPRx: VPR Extensions.- C.1 Determination of Router Effort.- C.2 Routing Graph and Netlist Changes (Sparse Clusters).- C.3 Area and Delay Calculation Improvements.- C.4 Runtime Improvements.- C.5 Experimental Noise Reduction.- C.6 Correctness Changes.- References.

About the author

David Lewis ist geschäftsführender Inhaber einer Beratungsfirma, zu deren Kunden so bekannte Unternehmen wie Disney, Amazon und IKEA gehören.

Summary

Programmable Logic Devices (PLDs) have become the key implementation medium for the vast majority of digital circuits designed today. While the highest-volume devices are still built with full-fabrication rather than field programmability, the trend towards ever fewer ASICs and more FPGAs is clear. This makes the field of PLD architecture ever more important, as there is stronger demand for faster, smaller, cheaper and lower-power programmable logic. PLDs are 90% routing and 10% logic. This book focuses on that 90% that is the programmable routing: the manner in which the programmable wires are connected and the circuit design of the programmable switches themselves. Anyone seeking to understand the design of an FPGA needs to become lit erate in the complexities of programmable routing architecture. This book builds on the state-of-the-art of programmable interconnect by providing new methods of investigating and measuring interconnect structures, as well as new programmable switch basic circuits. The early portion of this book provides an excellent survey of interconnec tion structures and circuits as they exist today. Lemieux and Lewis then provide a new way to design sparse crossbars as they are used in PLDs, and show that the method works with an empirical validation. This is one of a few routing architecture works that employ analytical methods to deal with the routing archi tecture design. The analysis permits interesting insights not typically possible with the standard empirical approach.

Product details

Authors Gu Lemieux, Guy Lemieux, David Lewis
Publisher Springer, Berlin
 
Languages English
Product format Paperback / Softback
Released 21.10.2010
 
EAN 9781441954152
ISBN 978-1-4419-5415-2
No. of pages 206
Dimensions 156 mm x 236 mm x 14 mm
Weight 379 g
Illustrations XX, 206 p. 12 illus.
Subjects Natural sciences, medicine, IT, technology > Technology > Electronics, electrical engineering, communications engineering

Elektrotechnik, C, Theoretische Informatik, computer science, engineering, Electrical Engineering, Theory of Computation, Electrical and Electronic Engineering, Tables, Circuits and Systems, Mathematical theory of computation, Electronic Circuits and Systems, system on chip (SoC)

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