High-Speed Clock Network Design

High-Speed Clock Network Design is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters.

List of contents

1 Introduction.- 2 Overview to Timing Constraints.- 3 Sequential Clocked Elements.- 4 Design Methodology for Domino Circuits.- 5 Clock Generation and De-Skewing.- 6 Microprocessor Clock Distribution Examples.- 7 Clock Network Simulation Methods.- 8 Low-Voltage Swing Clock Distribution.- 9 Routing Clock on Package.- 10 Balanced Clock Routing Algorithms.- 11 Clock Tree Design Flow in Asic.- Reference.

Summary

High-Speed Clock Network Design is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters.

Product details

• Authors: Qing K Zhu, Qing K. Zhu
• Publisher: Springer, Berlin
• Languages: English
• Product format: Paperback / Softback
• Released: 21.10.2010
• EAN: 9781441953360
• ISBN: 978-1-4419-5336-0
• No. of pages: 188
• Dimensions: 152 mm x 11 mm x 235 mm
• Weight: 306 g
• Illustrations: VIII, 188 p.
• Subjects: Natural sciences, medicine, IT, technology > Technology > Electronics, electrical engineering, communications engineering; Simulation, Elektrotechnik, B, Network, Computer-Aided Design (CAD), engineering, Electrical Engineering, Networks, layers, Electrical and Electronic Engineering, Circuits and Systems, Microprocessor, Computer-Aided Engineering (CAD, CAE) and Design, Computer-aided engineering, Electronic circuits, Electronic Circuits and Systems