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Sommario
Quotation ix
Preface xi
Introduction xv
Part 1. Characterization of a Semiconductor Memory 1
Chapter 1. Timing Characterization of a Semiconductor Random-Access Memory 3
1.1. Signal naming convention 3
1.2. Timing diagram 4
1.3. Standardization of memory timing 9
1.4. Measurement of a characteristic time 14
1.5. Fundamental times 14
1.6. Conclusion 20
Chapter 2. Other Characteristics of a Semiconductor Random-Access Memory 21
2.1. Electrical characteristics 21
2.2. Miscellaneous characteristics 30
2.3. Performance measurement 31
2.4. Memory testing 31
2.5. Conclusion 32
Chapter 3. Encapsulation 33
3.1. Generalities 33
3.2. Interconnection technologies 37
2 3.2.1. Micro-wiring 38
3.2.2. Automatic tape transfer 38
3.2.3. Flip-chip technology 38
3.3. Two-dimensional single-chip encapsulation 40
3.3.1. Pin and pad packages 41
3.3.2. Encapsulation on substrate 49
3.4. Advanced integrations 52
3.4.1. Multichip module 52
3.4.2. Associated concepts 53
3.4.3. 2.5D integration 55
3.4.4. Three-dimensional integration 55
3.4.5. 3.5D package 57
3.5. Technical characteristics 57
3.6. Electrical modeling 58
3.7. Memory module 59
3.7.1. Definition 59
3.7.2. Form factor 60
3.7.3. Connectivity 79
3.8. Conclusion 82
Chapter 4. Electronic Aspects of Interfacing 83
4.1. Transmission line 83
4.1.1. Modeling 84
4.1.2. Termination 85
4.2. Possible interconnection types 86
4.3. Reminder on the interface between two logical subassemblies 91
4.4. Equalization 98
4.5. Power supply 99
4.6. The SPMT interface 102
4.7. Conclusion 103
Part 2. Asynchronous Static Random-Access Memory 105
Chapter 5. Internal Organization of a Generic Asynchronous Static Random-Access Memory 107
5.1. Memory cell 108
5.2. General organization 123
5.3. Read amplifier 128
5.4. Basic operations 129
5.5. Layout 132
5.6. Manufacturing technologies 134
5.7. Cell stability 135
5.8. Conclusion 137
Chapter 6. Asynchronous Static Random-Access Memory as a Component 139
6.1. The asynchronous model 140 6.2. Variations on the asynchronous model 147
6.2.1. Serial-access SRAM 147
6.2.2. Backup memory 147
6.3. Conclusion 150 Conclusion 153
Appendices 157
Appendix 1 159
Appendix 2 165
List of Acronyms 171
References 193
Index 209
Info autore
Philippe Darche is Lecturer in Computer Science at the University Institute of Technology (IUT) of Paris - Rives de Seine and Researcher in the Distributed Algorithms and Systems (DeLyS) team at LIP6, Sorbonne University, France. He is also the author of fifteen books on computer architecture.
