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Having hit power limitations to even more aggressive out-of-order execution in processor cores, many architects in the past decade have turned to single-instruction-multiple-data (SIMD) execution to increase single-threaded performance. SIMD execution, or having a single instruction drive execution of an identical operation on multiple data items, was already well established as a technique to efficiently exploit data parallelism. Furthermore, support for it was already included in many commodity processors. However, in the past decade, SIMD execution has seen a dramatic increase in the set of applications using it, which has motivated big improvements in hardware support in mainstream microprocessors. The easiest way to provide a big performance boost to SIMD hardware is to make it wider-i.e., increase the number of data items hardware operates on simultaneously. Indeed, microprocessor vendors have done this. However, as we exploit more data parallelism in applications, certain challenges can negatively impact performance. In particular, conditional execution, non-contiguous memory accesses, and the presence of some dependences across data items are key roadblocks to achieving peak performance with SIMD execution. This book first describes data parallelism, and why it is so common in popular applications. We then describe SIMD execution, and explain where its performance and energy benefits come from compared to other techniques to exploit parallelism. Finally, we describe SIMD hardware support in current commodity microprocessors. This includes both expected design tradeoffs, as well as unexpected ones, as we work to overcome challenges encountered when trying to map real software to SIMD execution.
About the author
Christopher J.Hughes is a principal engineer at Intel Labs, where he joined in August 2003. He received his Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign in 2003, Master of Science degree in Computer Science from the University of Illinois at Urbana-Champaign in 2000, and Bachelor of Science degree in Electrical Engineering and Bachelor of Arts degree in Computer Science from Rice University in 1998. He led the teams that defined the gather instructions in Intel AVX2, the gather and scatter instructions in Intel AVX-512, and Intels AVX-512CD instructions. His research focuses on highly parallel architectures for compute- and data-intensive applications.
