Read more
System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing.The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowing to reduce the voltage on each core. Because dynamic power is proportional to the frequency and to the square of the voltage, we get a big gain, even though we may have more cores running. As more and more cores are integrated into these designs to share the ever increasing processing load, the main challenges lie in efficient memory hierarchy, scalable system interconnect, new programming paradigms, and efficient integration methodology for connecting such heterogeneous cores into a single system capable of leveraging their individual flexibility. Current design methods tend toward mixed HW/SW co-designs targeting multicore systems on-chip for specific applications. To decide on the lowest cost mix of cores, designers must iteratively map the device's functionality to a particular HW/SW partition and target architectures. In addition, to connect the heterogeneous cores, the architecture requires high performance complex communication architectures and efficient communication protocols, such as hierarchical bus, point-to-point connection, or Network-on-Chip. Software development also becomes far more complex due to the difficulties in breaking a single processing task into multiple parts that can be processed separately and then reassembled later. This reflects the fact that certain processor jobs cannot be easily parallelized to run concurrently on multiple processingcores and that load balancing between processing cores - especially heterogeneous cores - is very difficult.
About the author
Dr. Abderazek Ben Abdallah received his Ph.D. in computer engineering from The University of Electro-Communications in Tokyo in 2002. From April 2014to March 2022, he served as the Head of the Computer Engineering Division at the University of Aizu, Japan. Since April 2022, he has held the position of Dean at the School of Computer Science and Engineering at the University of Aizu. Currently, Dr. Ben Abdallah is a Full Professor at the University of Aizu. He is the author of four books and holds six registered and eight provisional Japanese patents. Additionally, he has published over 150 peer-reviewed journal articles and conference papers. His research interests span adaptive and self-organizing systems, neuromorphic computing, interconnection networks, and AI-powered cyber-physical systems. Dr. Ben Abdallah is a Senior Member of both the IEEE and ACM, reflecting his significant contributions to computer engineering.
Dr. Khanh N. Dang currently serves as an Associate Professor in the Department of Computer Science and Engineering at the University of Aizu. He earned his Ph.D. from the University of Aizu and his M.Sc. from the University of Paris XI. Dr. Dang has published numerous peer-reviewed journal articles and presented his work at various conferences. He is also the author of one book and holds several provisional patents in Japan. Dr. Dang's research areas include Network-on-Chips (NoC), 3DIntegrated Circuits (3D-ICs), neuromorphic computing, and fault-tolerant systems. Within these fields, he focuses on developing efficient communication architectures and enhancing the reliability and performance of multi-core processors. In neuromorphic computing, he explores the implementation of brain-inspired algorithms to create more efficient and intelligent systems. He is a member of IEEE.
Summary
System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing.
The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowing to reduce the voltage on each core. Because dynamic power is proportional to the frequency and to the square of the voltage, we get a big gain, even though we may have more cores running.
As more and more cores are integrated into these designs to share the ever increasing processing load, the main challenges lie in efficient memory hierarchy, scalable system interconnect, new programming paradigms, and efficient integration methodology for connecting such heterogeneous cores into a single system capable of leveraging their individual flexibility.
Current design methods tend toward mixed HW/SW co-designs targeting multicore systems on-chip for specific applications. To decide on the lowest cost mix of cores, designers must iteratively map the device’s functionality to a particular HW/SW partition and target architectures. In addition, to connect the heterogeneous cores, the architecture requires high performance complex communication architectures and efficient communication protocols, such as hierarchical bus, point-to-point connection, or Network-on-Chip.
Software development also becomes far more complex due to the difficulties in breaking a single processing task into multiple parts that can be processed separately and then reassembled later. This reflects the fact that certain processor jobs cannot be easily parallelized to run concurrently on multiple processingcores and that load balancing between processing cores – especially heterogeneous cores – is very difficult.
