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Klappentext When first published this text by David Johns and Kenneth Martin quickly became a leading textbook for the advanced course on Analog IC Design. This new edition has been thoroughly revised and updated but continues the central themes of the first edition which made it so sucessful. This edition features extensive new material on CMOS IC device modeling, processing and layout. Coverage has been added on several types of circuits that have increased in importance in the past decade, such as generalized integer-N phase locked loops and their phase noise analysis, voltage regulators, and 1.5b-per-stage pipelined A/D converters. Two new chapters have been added to make the book more accessible to beginners in the field: frequency response of analog ICs; and basic theory of feedback amplifiers. Zusammenfassung * The second edition of Analog Integrated Circuit Design focuses on several types of circuits that have increased in importance in the past decade. * The text is enhanced with material on CMOS IC device modeling, updated processing layout and expanded coverage to reflect technical innovations. Inhaltsverzeichnis CHAPTER 1 INTEGRATED-CIRCUIT DEVICES AND MODELLING 1 1.1 Semiconductors and pn Junctions 1 1.1.1 Diodes 2 1.1.2 Reverse-Biased Diodes 4 1.1.3 Graded Junctions 8 1.1.4 Large-Signal Junction Capacitance 10 1.1.5 Forward-Biased Junctions 11 1.1.6 Junction Capacitance of Forward-Biased Diode 12 1.1.7 Small-Signal Model of a Forward-Biased Diode 13 1.1.8 Schottky Diodes 14 1.2 MOS Transistors 15 1.2.1 Symbols for MOS Transistors 16 1.2.2 Basic Operation 17 1.2.3 Large-Signal Modelling 22 1.2.4 Body Effect 25 1.2.5 p-Channel Transistors 26 1.2.6 Low-Frequency Small-Signal Modelling in the Active Region 26 1.2.7 High-Frequency Small-Signal Modelling in the Active Region 32 1.2.8 Small-Signal Modelling in the Triode and Cutoff Regions 35 1.2.9 Analog Figures of Merit and Trade-offs 37 1.3 Device Model Summary 39 1.3.1 Constants 40 1.3.2 Diode Equations 40 1.3.3 MOS Transistor Equations 41 1.4 Advanced MOS Modelling 43 1.4.1 Subthreshold Operation 43 1.4.2 Mobility Degradation 46 1.4.3 Summary of Subthreshold and Mobility Degradation Equations 48 1.4.4 Parasitic Resistances 48 1.4.5 Short-Channel Effects 49 1.4.6 Leakage Currents 50 1.5 SPICE Modelling Parameters 51 1.5.1 Diode Model 51 1.5.2 MOS Transistors 52 1.5.3 Advanced SPICE Models of MOS Transistors 52 1.6 Passive Devices 55 1.6.1 Resistors 55 1.6.2 Capacitors 59 1.7 Appendix 61 1.7.1 Diode Exponential Relationship 61 1.7.2 Diode-Diffusion Capacitance 63 1.7.3 MOS Threshold Voltage and the Body Effect 65 1.7.4 MOS Triode Relationship 67 1.8 Key Points 69 1.9 References 70 1.10 Problems 70 CHAPTER 2 PROCESSING AND LAYOUT 73 2.1 CMOS Processing 73 2.1.1 The Silicon Wafer 73 2.1.2 Photolithography and Well Definition 74 2.1.3 Diffusion and Ion Implantation 76 2.1.4 Chemical Vapor Deposition and Defining the Active Regions 78 2.1.5 Transistor Isolation 78 2.1.6 Gate-Oxide and Threshold-Voltage Adjustments 81 2.1.7 Polysilicon Gate Formation 82 2.1.8 Implanting the Junctions, Depositing SiO2, and Opening Contact Holes 82 2.1.9 Annealing, Depositing and Patterning Metal, and Overglass Deposition 84 2.1.10 Additional Processing Steps 84 2.2 CMOS Layout and Design Rules 86 2.2.1 Spacing Rules 86 2.2.2 Planarity and Fill Requirements 94 2.2.3 Antenna Rules 94 2.2.4 Latch-Up 95 2.3 Variability and Mismatch 96 2.3.1 Systematic Variations Including Prox...
