System-on-a-Chip Verification - Methodology and Techniques

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:

1. Explanation of the objective involved in performing verification after a given design step;
2. Features of options available;
3. When to use a particular option;
4. How to select an option; and
5. Limitations of the option.

This exciting new book will be of interest to all designers and test professionals.

Table des matières

System-level Verification.- Block-level Verification.- Analog/Mixed Signal Simulation.- Simulation.- Hardware/Software Co-verification.- Static Netlist Verification.- Physical Verification and Design Sign-off.

Résumé

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:

1. Explanation of the objective involved in performing verification after a given design step;
2. Features of options available;
3. When to use a particular option;
4. How to select an option; and
5. Limitations of the option.

This exciting new book will be of interest to all designers and test professionals.

Détails du produit

• Auteurs: Pete Paterson, Peter Paterson, Prakas Rashinkar, Prakash Rashinkar, Leena Singh
• Edition: Springer Netherlands
• Langues: Anglais
• Format d'édition: Livre Relié
• Sortie: 14.04.2009
• EAN: 9780792372790
• ISBN: 978-0-7923-7279-0
• Pages: 372
• Dimensions: 160 mm x 241 mm x 26 mm
• Poids: 751 g
• Illustrations: XX, 372 p. 22 illus.
• Catégories: Sciences naturelles, médecine, informatique, technique > Technique > Electronique, électrotechnique, technique de l'information; Simulation, Elektrotechnik, C, Model, Künstliche Intelligenz, Artificial Intelligence, Computer-Aided Design (CAD), engineering, Verification, Electrical Engineering, Electrical and Electronic Engineering, Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design, Computer-aided engineering, Electronic Circuits and Systems, model checking, system on chip (SoC)